1. Field of the Invention
The present invention relates to memory cell architecture. More particularly, the present invention relates to optimizing memory cell architecture through optimization of memory cell structure.
2. Description of the Related Art
Read only memory (ROM) is a data storage device used in a variety of electrical systems. Generally, data stored in ROM is permanently fixed; that is, the data is nonvolatile. Data is stored in ROM through a variety of programming methods. In certain applications, ROM storage devices are used to implement specific logic functions for various applications, such as programs or processes. One traditional approach to function implementation determines the function output for all possible input combinations (ROM-Based Computation). In this approach, rather than evaluating a logic function in real time, function output is read from memory where all possible outputs are pre-stored. This approach is commonly seen in applications such as Field Programmable Gate Array (FPGA) architecture, and is used to implement basic logic gates such as NAND, NOR, XOR, or even 1 bit full adder. Large functions can also be implemented using this basic cell structure, but the approach is usually slower than conventional logic designs. Further, since a large memory size (2N×O bits; where N is the number of inputs, and O the number of outputs) is required to implement large functions using a single look-up table, straight-forward implementation of large functions is also not feasible in terms of speed, memory size, and power consumption. Accordingly, what is needed is a memory cell structure that enables implementation of high performance logic functions and benefits from improved performance, reduced memory size and lower power consumption.